1. Field of the Invention
The present invention relates to memory devices and memory systems. More particularly, the invention relates to low power interfaces for use in memory devices and memory systems.
2. Description of the Related Art
In order to achieve high data bandwidth, some memory devices, such as synchronous dynamic random access memories (DRAMs) and Rambus(copyright) DRAMs, use high-speed electrical signaling, such as Rambus(copyright) Signaling Level (RSL), and clocked interfaces that pipeline the logic and datapaths to and from the core. Rambus(copyright) DRAMs are licensed by Rambus, Inc., Mountain View, Calif. For these synchronous interfaces, power becomes an important issue, particularly at high frequencies. High power consumption can exceed thermal cooling limits of the package or system or cause excessive battery drain in portable devices. Thus, it becomes important to manage this power optimally in a way that maximizes performance and minimizes system cost.
To manage power in these devices, various power modes can be used for the interface, each with different power consumption and turn-on latencies. Clocks can be divided into different xe2x80x9cclock domainsxe2x80x9d and controlled with clock gating. Clock recovery circuits, such as delay locked loops (DLLs) or phase-locked loops (PLLs), can have different modes, each with different power and turn-on latencies. Receiver circuits for high-speed signaling often consume both direct current (DC) and alternating current (AC) power and can be separately controlled.
A memory device can have low power modes, in which the high power receiver circuits are turned off, internal interface clocks are disabled, and internal clock compensation circuits are turned off or placed in a nap state. Nap represents a state where portions of the internal clock compensation circuits are turned off to reduce power and some portions are left on so that phase information is stored. Nap is an intermediate state between fully on and off, in which the power consumption is lower than full on; exit latency from the Nap state is much less than the exit latency from the full off state.
For power modes with very low power consumption, high-speed signaling receivers can consume a relatively large portion of device power. With memory devices that only use a high-speed input/output (I/O) interface, at minimum, some portion of the receivers must be left on in order for the device to receive a command to exit from the low power mode.
A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device.